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Publications

Rossi, Daniele, Omana, Martin, Metra, Cecilia and Paccagnella, Alessandro (2014) Impact of bias temperature instability on soft error susceptibility. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-9. (doi:10.1109/TVLSI.2014.2320307).

Omana, Martin, Rossi, Daniele, Giaffreda, Daniele, Metra, Cecilia, Mak, T.M., Raman, Asifur and Tam, Simon (2014) Low-cost on-chip clock jitter measurement scheme. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-9. (doi:10.1109/TVLSI.2014.2312431).

Rossi, Daniele, Omana, Martin, Giaffreda, Daniele and Metra, Cecilia (2014) Modeling and detection of hot-spot in shaded photovoltaic cells. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-9. (doi:10.1109/TVLSI.2014.2333064).

Rossi, Daniele, Omana, Martin, Cazeaux, Jose' Manuel and Mak, T.M. (2014) Clock faults induced min and max delay violations. Journal of Electronic Testing Theory and Applications (JETTA), 30, (1), 111-123. (doi:10.1007/s10836-013-5426-4).

Omana, Martin, Rossi, Daniele, Giaffreda, Daniele, Specchia, Roberto, Metra, Cecilia, Marzencki, Marcin and Kaminska, Bozena (2013) Faults affecting energy harvesting circuits of self-powered wireless sensors and their possible concurrent detection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, (12), 2286-2294. (doi:10.1109/TVLSI.2012.2230036).

Vimalathithan, R., Rossi, Daniele, Omana, Martin, Metra, Cecilia and Valarmathi, M. L. (2013) Polynomial based key distribution scheme for WPAN. Malaysian Journal of Mathematical Sciences, 7, (S), 59-72.

Rossi, Daniele, Omana, Martin, Garrammone , Giuliano, Metra, Cecilia and Jas, Abhijit (2013) Low cost concurrent error detection strategy for the control logic of high performance microprocessor RAS improvement. Journal of Electronic Testing Theory and Applications (JETTA), 29, 401-413. (doi:10.1007/s10836-013-5355-2).

Omana, Martin, Rossi, Daniele, Bosio, Nicolo' and Metra, Cecilia (2013) Low cost NBTI degradation detection and masking approaches. IEEE Transactions on Computers, 62, (3), 496-509. (doi:10.1109/TC.2011.246).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2010) High performance robust latches. IEEE Transactions on Computers, 59, (11), 1455-1465. (doi:10.1109/TC.2010.24).

Rossi, Daniele and Metra, Cecilia (2003) Error correcting strategy for high speed and high density reliable flash memories. Journal of Electronic Testing: Theory and Applications (JETTA), 19, (5), 511-521. (doi:10.1023/A:1025117828910).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2004) Model for transient fault susceptibility of combinational circuits. Journal of Electronic Testing: Theory and Applications (JETTA), 20, (5), 501-509. (doi:10.1023/B:JETT.0000042514.37566.6d).

Rossi, Daniele, Nieuwland, Andre, Katoch, Atul and Metra, Cecilia (2005) Exploiting ECC redundancy to minimize crosstalk impact. IEEE Design & Test of Computers, 22, (1), 59-70. (doi:10.1109/MDT.2005.10).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2005) Low cost and high speed embedded two-rail code checker. IEEE Transactions on Computers, 54, (2), 153-164. (doi:10.1109/TC.2005.30).

Cazeaux, Manuel, Rossi, Daniele and Metra, Cecilia (2005) Self-checking voter for high speed TMR systems. Journal of Electronic Testing: Theory and Applications (JETTA), 21, (4), 377-389. (doi:10.1007/s10836-005-0838-4).

Rossi, Daniele, Nieuwland, Andre, Katoch, Atul and Metra, Cecilia (2005) New ECC for crosstalk impact minimization. IEEE Design & Test of Computers, 22, (4), 340-348. (doi:10.1109/MDT.2005.91).

Metra, Cecilia, Rossi, Daniele and Mak, T.M. (2007) Won’t on-chip clock calibration guarantee performance boost and product quality? IEEE Transactions on Computers, 56, (3), 415-428. (doi:10.1109/TC.2007.53).

Rossi, Daniele, Cazeaux, Jose Manuel and Metra, Cecilia (2007) Modeling crosstalk effects in CNT bus architectures. IEEE Transactions on Nanotechnology, 6, (2), 133-145. (doi:10.1109/TNANO.2007.891814).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2007) Latch susceptibility to transient faults and new hardening approach. IEEE Transactions on Computers, 56, (9), 1255-1268. (doi:10.1109/TC.2007.1070).

Rossi, Daniele, Niewland, Andre' and Metra, Cecilia (2008) Simultaneous switching noise: the relation between bus layout and coding. IEEE Design & Test of Computers, 25, (1), 76-86. (doi:10.1109/MDT.2008.25).

Rossi, Daniele, Nieuwland, Andre', Van Dijk, V.E.S., Kleihorst, Richard and Metra, Cecilia (2008) Power consumption of fault tolerant busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6, (5), 542-553. (doi:10.1109/TVLSI.2008.917535).

Rossi, Daniele, Omana, Martin and Metra, Cecilia (2008) Checkers' no-harm alarms and design approaches to tolerate them. Journal of Electronic Testing Theory and Applications (JETTA), 24, (1-3), 93-103. (doi:10.1007/s10836-007-5031-5).

Rossi, Daniele, Cazeaux, Jose' Manuel, Omana, Martin, Metra, Cecilia and Chatterjee, Abhijit (2009) Accurate linear model for SET critical charge estimation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17, (8), 1161-1166. (doi:10.1109/TVLSI.2009.2020391).

Rossi, Daniele, Metra, Cecilia and Ricco', Bruno (2002) Fast and compact error correcting scheme for reliable multilevel flash memories. In, 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), Isle of Bendor , FR, , 221-225. (doi:10.1109/MTDT.2002.1029759).

Rossi, Daniele, Van Dijk, V.E.S., Kleihorst, Richard, Nieuwland, Andre' and Metra, Cecilia (2002) Coding scheme for low energy consumption fault tolerant bus. In, 8th IEEE International On-Line Testing Workshop, Isle of Bendor , FR, , 8-12. (doi:10.1109/OLT.2002.1030176).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2003) High speed and highly testable parallel two-rail code checker. In, IEEE/ACM Design, Automation and Test in Europe Conference, Munich, DE, 03 - 07 Mar 2003. , 608-613. (doi:10.1109/DATE.2003.10078).

Omana, Martin, Papasso, Giacinto, Rossi, Daniele and Metra, Cecilia (2003) A model for transient fault propagation in combinatorial logic. In, 9th IEEE International On-Line Testing Symposium, Kos, Greece, 07 - 09 Jul 2003. , 111-115. (doi:10.1109/OLT.2003.1214376).

Di Silvio, Luca, Rossi, Daniele and Metra, Cecilia (2003) Crosstalk effect minimization for encoded busses. In, 9th IEEE International On-Line Testing Symposium, Kos, Greece, 07 - 09 Jul 2003. Institute of Electrical and Electronics Engineers, 214-218. (doi:10.1109/OLT.2003.1214401).

Rossi, Daniele, Van Dijk, V.E.S., Kleihorst, Richard, Nieuwland, Andre' and Metra, Cecilia (2003) Power consumption of fault tolerant codes: the active elements. In, 9th IEEE International On-Line Testing Symposium, Kos, Greece, 07 - 09 Jul 2003. , 61-67. (doi:10.1109/OLT.2003.1214368).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2003) Novel transient fault hardened static latch. In, Proceedings. ITC 2003. International Test Conference, Bologna, IT, 30 Sep - 02 Oct 2003. Baltimore, US, IEEE, 886-892. (doi:10.1109/TEST.2003.1271074).

Metra, Cecilia, Mak, T.M. and Rossi, Daniele (2003) Clock calibration faults and their impact on quality of high performance microprocessors. In, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, US, 03 - 05 Nov 2003. Institute of Electrical and Electronics Engineers, 63-70. (doi:10.1109/DFTVS.2003.1250096).

Rossi, Daniele, Cavallotti, Stefano and Metra, Cecilia (2003) Error correcting codes for crosstalk effect minimization [system buses]. In, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, US, 03 - 05 Nov 2003. IEEE, 257-264. (doi:10.1109/DFTVS.2003.1250120).

Cazeaux, Jose' Manuel, Rossi, Daniele and Metra, Cecilia (2004) New high speed CMOS self-checking voter. In, 10th IEEE International On-Line Testing Symposium (IOLTS 2004). Proceedings, Funchal, PT, 12 Jul 2004 - 14 Jul 2014 . IEEE, 58-63. (doi:10.1109/OLT.2004.1319660).

Rossi, Daniele, Muccio, Andrea, Nieuwland, Andre, Katoch, Atul and Metra, Cecilia (2004) Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems [error correcting codes]. In, 10th IEEE International On-Line Testing Symposium (IOLTS 2004). Proceedings, Funchal, PT, 11 - 14 Jul 2004. IEEE, 135-140. (doi:10.1109/OLT.2004.1319671).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2004) Fast and low-cost clock deskew buffer. In, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2004). Proceedings, Cannes, FR, 10 - 13 Oct 2004. IEEE, 202-210. (doi:10.1109/DFTVS.2004.1347841).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2005) Low cost scheme for on-line clock skew compensation. In, 23rd IEEE VLSI Test Symposium. Proceedings, Palm Springs, US, 01 - 05 May 2005. IEEE, 90-95. (doi:10.1109/VTS.2005.52).

Nieuwland, Andre, Katoch, Atul, Rossi, Daniele and Metra, Cecilia (2005) Coding techniques for low switching noise in fault tolerant busses. In, 11th IEEE International On-Line Testing Symposium, Saint Raphael, France, 06 - 08 Jul 2005. , 183-189. (doi:10.1109/IOLTS.2005.19).

Cazeaux, Jose Manuel, Rossi, Daniele, Omana, Martin, Chatterjee, Abhijit and Metra, Cecilia (2005) On-transistor level gate sizing for increased robustness to transient faults. In, 11th IEEE International On-Line Testing Symposium (IOLTS 2005), Saint Raphael, FR, 06 - 08 Jul 2005. IEEE, 23-28. (doi:10.1109/IOLTS.2005.49).

Metra, Cecilia, Omana, Martin, Rossi, Daniele, Cazeaux, Jose' Manuel and Mak, T.M. (2005) The other side of the timing equation: a result of clock faults. In, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), Monterey, US, 03 - 05 Oct 2005. , 169-177. (doi:10.1109/DFTVS.2005.65).

Rossi, Daniele, Omana, Martin, Toma, Fabio and Metra, Cecilia (2005) Multiple transient faults in logic: an issue for next generation ICs? In, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), Monterey, US, 03 - 05 Oct 2005. IEEE, 352-360. (doi:10.1109/DFTVS.2005.47).

Omana, Martin, Cazeaux, Jose Manuel, Rossi, Daniele and Metra, Cecilia (2006) Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. In, Design, Automation and Test in Europe (DATE '06). Proceedings, Munich, DE, 06 - 10 Mar 2006. IEEE, 170-175. (doi:10.1109/DATE.2006.244061).

Rossi, Daniele, Steiner, Carlo and Metra, Cecilia (2006) Analysis of the impact of bus implemented EDCs on on-chip SSN. In, Design, Automation and Test in Europe (DATE '06). Proceedings. Volume 1, Munich, DE, 06 - 10 Mar 2006. IEEE, 59-64. (doi:10.1109/DATE.2006.243982).

Metra, Cecilia, Rossi, Daniele, Omana, Martin, Cazeaux, Jose' Manuel and Mak, T.M. (2006) Can clock faults be detected through functional test? In, 2006 IEEE Design & Diagnostics in Electronic Circuits and Systems, Prague, CZ, 18 - 21 Apr 2006. Institute of Electrical and Electronics Engineers, 168-171. (doi:10.1109/DDECS.2006.1649606).

Metra, Cecilia, Omana, Martin, Rossi, Daniele and Cazeaux, Jose Manuel (2006) Path (min) delay faults and their impact on self-checking circuits’ operation. In, 12th IEEE International On-Line Testing Symposium, 2006. IOLTS 2006, Como, IT, , 17-22. (doi:10.1109/IOLTS.2006.47).

Rossi, Daniele, Omana, Martin, Metra, Cecilia and Pagni , Andrea (2006) Checker no-harm alarm robustness. In, 12th IEEE International On-Line Testing Symposium (IOLTS 2006), Como, IT, 10 - 12 Jul 2006. IEEE, 275-280. (doi:10.1109/IOLTS.2006.16).

Rossi, Daniele, Cazeaux, Jose' Manuel, Metra, Cecilia and Lombardi, Fabrizio (2006) A novel dual-walled CNT bus architecture with reduced cross-coupling features. In, Sixth IEEE Conference on Nanotechnology (IEEE-NANO 2006), Cincinnati, US, 17 - 20 Jun 2006. , 258-261. (doi:10.1109/NANO.2006.247623).

Rossi, Daniele, Angelini, Paolo and Metra, Cecilia (2007) Configurable error control scheme for NoC signal integrity. In, 13th IEEE International On-Line Testing Symposium, Crete, GR, 08 - 11 Jul 2007. , 43-48. (doi:10.1109/IOLTS.2007.24).

Metra, Cecilia, Rossi, Daniele, Omana, Martin, Jas, Abhijit and Galivanche, Rajesh (2008) Function-inherent code checking: a new low cost on-line testing approach for high performance microprocessor control logic. In, IEEE European Test Symposium, Verbania, Italy, 25 - 29 May 2008. , 171-176. (doi:10.1109/ETS.2008.24).

Rossi, Daniele, Angelini, Paolo, Metra, Cecilia, Campardo, Giovanni and Vanalli, G. P. (2008) Risks for signal integrity in system in package and possible rmedies. In, IEEE European Test Symposium, Verbania, Italy, 25 - 29 May 2008. , 165-170. (doi:10.1109/ETS.2008.23).

Ma, X., Huang, F., Chiminazzo, Federica, Rossi, Daniele, Metra, Cecilia and Lombardi, Fabrizio (2008) Resistive crossbar switching networks for inherently fault tolerant nano LUTs. In, 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, Cambridge, US, 29 - 30 Sep 2008. , 21-24. (doi:10.1109/NDCS.2008.21).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2009) Novel high speed robust latch. In, 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Chicago, US, 07 - 09 Oct 2009. , 65-73. (doi:10.1109/DFT.2009.40).

Omana, Martin, Rossi, Daniele, Bosio, Nicolo' and Metra, Cecilia (2010) Novel low-cost aging sensor. At CF '10 Proceedings of the 7th ACM international conference on Computing frontiers , Bertinoro, IT, 17 - 19 May 2010. , 93-94. (doi:10.1145/1787275.1787299).

Rossi, Daniele, Omana, Martin, Berghella, Gianluca, Metra, Cecilia, Chandra, Tirumurti and Galivanche, Rajesh (2010) Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. In, ACM International Conference on Computing Frontiers, Bertinoro, IT, 17 - 19 May 2010. , 113-114.

Omana, Martin, Rossi, Daniele, Bosio, Nicolo' and Metra, Cecilia (2010) Self-checking monitor for NBTI due degradation. In, IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, Montpellier, FR, 07 - 09 Jun 2010. , 1-6. (doi:10.1109/IMS3TW.2010.5503006).

Rossi, Daniele, Omana, Martin, Giaffreda, Daniele and Metra, Cecilia (2010) Secure communication protocol for wireless sensor networks. In, 8th IEEE East-West Design & Test Symposium (EWDTS), St. Petersburg, Russia, 17 - 20 Sep 2010. , 17-20. (doi:10.1109/EWDTS.2010.5742155).

Rossi, Daniele, Omana, Martin and Metra, Cecilia (2010) Transient fault and soft error on-die monitoring scheme. In, 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Kyoto, JP, 06 - 08 Oct 2010. , 391-398. (doi:10.1109/DFT.2010.53).

Rossi, Daniele, Timoncini, Nicola, Spica, Michael and Metra, Cecilia (2011) Error correcting code analysis for cache memory high reliability and performance. In, IEEE/ACM Design, Automation and Test in Europe (DATE), Grenoble, FR, 14 - 18 Mar 2011. , 1-6. (doi:10.1109/DATE.2011.5763257).

Giaffreda, Daniele, Omana, Martin, Rossi, Daniele and Metra, Cecilia (2011) Model for thermal behavior of shaded PV cells under hot-spot condition. In, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Vancouver, CA, 03 - 05 Oct 2011. , 252-258. (doi:10.1109/DFT.2011.47).

Rossi, Daniele, Omana, Martin, Metra, Cecilia and Paccagnella, Alessandro (2011) Impact of aging phenomena on soft error susceptibility. In, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Vancouver, CA, 03 - 05 Oct 2011. , 18-24. (doi:10.1109/DFT.2011.45).

Omana, Martin, Rossi, Daniele, Collepalumbo, Giacomo, Metra, Cecilia and Lombardi, Fabrizio (2012) Faults affecting the control blocks of PV arrays and techniques for their concurrent detection. In, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Austin, US, 03 - 05 Oct 2012. , 199-204. (doi:10.1109/DFT.2012.6378224).

Bolchini, C., Miele, A., Sandionigi, C., Ottavi, M., Pontarelli, S., Salsano, A, Metra, C., Omana, M., Rossi, D., Sonza Reorda, M., Sterpone, L., Violante, M., Gerardin, S., Bagattin, M. and Paccagnella, A. (2012) High-reliability fault tolerant digital systems in nanometric technologies: characterization and design methodologies. In, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Austin, US, 03 - 05 Oct 2012. , 121-125. (doi:10.1109/DFT.2012.6378211).

Omana, Martin, Rossi, Daniele, Fuzzi, Filippo, Metra, Cecilia, Tirumurti, Chandra and Galivanche, Rajesh (2013) Novel approach to reduce power droop during scan-based logic BIST. In, 18th IEEE European Test Symposium (ETS), Avignon, FR, 27 - 30 May 2013. , 1-6. (doi:10.1109/ETS.2013.6569375).

Rossi, Daniele, Tenentes, Vasileios, Khursheed, Saqib and Al-Hashimi, Bashir (2015) NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating. In, IEEE European Test Symposium 2015, Cluj-Napoca, RO, 25 - 29 May 2015.

Rossi, Daniele, Tenentes, Vasileios, Khursheed, Saqib and Al-Hashimi, Bashir M. (2015) BTI and leakage aware dynamic voltage scaling for reliable low power cache memories. In, 21st IEEE International On-Line Testing Symposium, Halkidiki, Greece, 06 - 08 Jul 2015. 6pp.

Tenentes, Vasileios, Rossi, Daniele, Khursheed, Saqib and Al-Hashimi, Bashir M. (2015) Diagnosis of power switches with power-distribution-network consideration. In, 20th IEEE European Test Symposium (ETS 2015), Cluj-Napoca, RO, 25 - 29 May 2015. 6pp.

Omana, Martin, Rossi, Daniele, Beniamino , Edda, Metra, Cecilia, Tirumurti, Chandra and Galivanche, Rajesh (2014) Power droop reduction during Launch-On-Shift scan-based logic BIST. In, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Amsterdam, NL, 01 - 03 Oct 2014. IEEE6pp, 21-26. (doi:10.1109/DFT.2014.6962063).

Tenentes, Vasileios, Khursheed, Saqib, Rossi, Daniele, Yang, Sheng and Al-Hashimi, Bashir M. (2015) DFT architecture with power-distribution-network consideration for delay-based power gating test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1-12. (doi:10.1109/TCAD.2015.2446939).

Rossi, Daniele, Tenentes, Vasileios, Yang, Sheng, Khursheed, Saqib and Al-Hashimi, Bashir (2015) Reliable power gating with NBTI aging benefits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-10.

Rossi, Daniele, Tenentes, Vasileios, Yang, Sheng, Khursheed, Saqib and Al-Hashimi, Bashir (2016) Aging benefits in nanometer CMOS designs. IEEE Transactions on Circuits and Systems II Express Briefs, 1-5.

Omana, Martin, Rossi, Daniele, Edara, TusharaSandeep and Metra, Cecilia (2015) Impact of aging phenomena on Latches’ robustness. IEEE Transactions on Nanotechnology, 15, (2), 129-136. (doi:10.1109/TNANO.2015.2494612).

Omana, Martin, Rossi, Daniele, Beniamino, Edda, Metra, Cecilia, Tirumurti, Chandrasekharan and Galivanche, Rajesh (2015) Low-cost and high-reduction approaches for power droop during launch-on-shift scan-based logic BIST. IEEE Transactions on Computers, 1-12. (doi:10.1109/TC.2015.2490058).

Halak, Basel, Rossi, Daniele and Jiajing , Cai (2016) Analysis of BTI aging of level shifters. In, 22nd IEEE International Symposium on On-Line Testing and Robust System Design ieee.

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