The University of Southampton

Publications

Rossi, Daniele, Omana, Martin, Metra, Cecilia and Paccagnella, Alessandro (2014) Impact of bias temperature instability on soft error susceptibility IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-9. (doi:10.1109/TVLSI.2014.2320307).

Omana, Martin, Rossi, Daniele, Giaffreda, Daniele, Metra, Cecilia, Mak, T.M., Raman, Asifur and Tam, Simon (2014) Low-cost on-chip clock jitter measurement scheme IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-9. (doi:10.1109/TVLSI.2014.2312431).

Rossi, Daniele, Omana, Martin, Giaffreda, Daniele and Metra, Cecilia (2014) Modeling and detection of hot-spot in shaded photovoltaic cells IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-9. (doi:10.1109/TVLSI.2014.2333064).

Rossi, Daniele, Omana, Martin, Cazeaux, Jose' Manuel and Mak, T.M. (2014) Clock faults induced min and max delay violations Journal of Electronic Testing, Theory and Applications (JETTA), 30, (1), pp. 111-123. (doi:10.1007/s10836-013-5426-4).

Omana, Martin, Rossi, Daniele, Giaffreda, Daniele, Specchia, Roberto, Metra, Cecilia, Marzencki, Marcin and Kaminska, Bozena (2013) Faults affecting energy harvesting circuits of self-powered wireless sensors and their possible concurrent detection IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, (12), pp. 2286-2294. (doi:10.1109/TVLSI.2012.2230036).

Vimalathithan, R., Rossi, Daniele, Omana, Martin, Metra, Cecilia and Valarmathi, M. L. (2013) Polynomial based key distribution scheme for WPAN Malaysian Journal of Mathematical Sciences, 7, (S), pp. 59-72.

Rossi, Daniele, Omana, Martin, Garrammone, Giuliano, Metra, Cecilia, Jas, Abhijit and Galivanche, Rajesh (2013) Low cost concurrent error detection strategy for the control logic of high performance microprocessor RAS improvement Journal of Electronic Testing, Theory and Applications (JETTA), 29, pp. 401-413. (doi:10.1007/s10836-013-5355-2).

Omana, Martin, Rossi, Daniele, Bosio, Nicolo' and Metra, Cecilia (2013) Low cost NBTI degradation detection and masking approaches IEEE Transactions on Computers, 62, (3), pp. 496-509. (doi:10.1109/TC.2011.246).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2010) High performance robust latches IEEE Transactions on Computers, 59, (11), pp. 1455-1465. (doi:10.1109/TC.2010.24).

Rossi, Daniele and Metra, Cecilia (2003) Error correcting strategy for high speed and high density reliable flash memories Journal of Electronic Testing, Theory and Applications (JETTA), 19, (5), pp. 511-521. (doi:10.1023/A:1025117828910).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2004) Model for transient fault susceptibility of combinational circuits Journal of Electronic Testing, Theory and Applications (JETTA), 20, (5), pp. 501-509. (doi:10.1023/B:JETT.0000042514.37566.6d).

Rossi, Daniele, Nieuwland, Andre, Katoch, Atul and Metra, Cecilia (2005) Exploiting ECC redundancy to minimize crosstalk impact IEEE Design & Test of Computers, 22, (1), pp. 59-70. (doi:10.1109/MDT.2005.10).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2005) Low cost and high speed embedded two-rail code checker IEEE Transactions on Computers, 54, (2), pp. 153-164. (doi:10.1109/TC.2005.30).

Cazeaux, Manuel, Rossi, Daniele and Metra, Cecilia (2005) Self-checking voter for high speed TMR systems Journal of Electronic Testing, Theory and Applications (JETTA), 21, (4), pp. 377-389. (doi:10.1007/s10836-005-0838-4).

Rossi, Daniele, Nieuwland, Andre, Katoch, Atul and Metra, Cecilia (2005) New ECC for crosstalk impact minimization IEEE Design & Test of Computers, 22, (4), pp. 340-348. (doi:10.1109/MDT.2005.91).

Metra, Cecilia, Rossi, Daniele and Mak, T.M. (2007) Won’t on-chip clock calibration guarantee performance boost and product quality? IEEE Transactions on Computers, 56, (3), pp. 415-428. (doi:10.1109/TC.2007.53).

Rossi, Daniele, Cazeaux, Jose Manuel, Metra, Cecilia and Lombardi, Fabrizio (2007) Modeling crosstalk effects in CNT bus architectures IEEE Transactions on Nanotechnology, 6, (2), pp. 133-145. (doi:10.1109/TNANO.2007.891814).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2007) Latch susceptibility to transient faults and new hardening approach IEEE Transactions on Computers, 56, (9), pp. 1255-1268. (doi:10.1109/TC.2007.1070).

Rossi, Daniele, Niewland, Andre' and Metra, Cecilia (2008) Simultaneous switching noise: the relation between bus layout and coding IEEE Design & Test of Computers, 25, (1), pp. 76-86. (doi:10.1109/MDT.2008.25).

Rossi, Daniele, Nieuwland, Andre', Van Dijk, V.E.S., Kleihorst, Richard and Metra, Cecilia (2008) Power consumption of fault tolerant busses IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6, (5), pp. 542-553. (doi:10.1109/TVLSI.2008.917535).

Rossi, Daniele, Omana, Martin and Metra, Cecilia (2008) Checkers' no-harm alarms and design approaches to tolerate them Journal of Electronic Testing, Theory and Applications (JETTA), 24, (1-3), pp. 93-103. (doi:10.1007/s10836-007-5031-5).

Rossi, Daniele, Cazeaux, Jose' Manuel, Omana, Martin, Metra, Cecilia and Chatterjee, Abhijit (2009) Accurate linear model for SET critical charge estimation IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17, (8), pp. 1161-1166. (doi:10.1109/TVLSI.2009.2020391).

Rossi, Daniele, Metra, Cecilia and Ricco', Bruno (2002) Fast and compact error correcting scheme for reliable multilevel flash memories At 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), France. , pp. 221-225. (doi:10.1109/MTDT.2002.1029759).

Rossi, Daniele, Van Dijk, V.E.S., Kleihorst, Richard, Nieuwland, Andre' and Metra, Cecilia (2002) Coding scheme for low energy consumption fault tolerant bus At 8th IEEE International On-Line Testing Workshop, France. , pp. 8-12. (doi:10.1109/OLT.2002.1030176).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2003) High speed and highly testable parallel two-rail code checker At IEEE/ACM Design, Automation and Test in Europe Conference, Germany. 03 - 07 Mar 2003. , pp. 608-613. (doi:10.1109/DATE.2003.10078).

Omana, Martin, Papasso, Giacinto, Rossi, Daniele and Metra, Cecilia (2003) A model for transient fault propagation in combinatorial logic At 9th IEEE International On-Line Testing Symposium, Greece. 07 - 09 Jul 2003. , pp. 111-115. (doi:10.1109/OLT.2003.1214376).

Di Silvio, Luca, Rossi, Daniele and Metra, Cecilia (2003) Crosstalk effect minimization for encoded busses At 9th IEEE International On-Line Testing Symposium, Greece. 07 - 09 Jul 2003. , pp. 214-218. (doi:10.1109/OLT.2003.1214401).

Rossi, Daniele, Van Dijk, V.E.S., Kleihorst, Richard, Nieuwland, Andre' and Metra, Cecilia (2003) Power consumption of fault tolerant codes: the active elements At 9th IEEE International On-Line Testing Symposium, Greece. 07 - 09 Jul 2003. , pp. 61-67. (doi:10.1109/OLT.2003.1214368).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2003) Novel transient fault hardened static latch At Proceedings. ITC 2003. International Test Conference, Italy. 30 Sep - 02 Oct 2003. , pp. 886-892. (doi:10.1109/TEST.2003.1271074).

Metra, Cecilia and Mak, T.M. (2003) Clock calibration faults and their impact on quality of high performance microprocessors At 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, United States. 03 - 05 Nov 2003. , pp. 63-70. (doi:10.1109/DFTVS.2003.1250096).

Rossi, Daniele, Cavallotti, Stefano and Metra, Cecilia (2003) Error correcting codes for crosstalk effect minimization [system buses] At 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, United States. 03 - 05 Nov 2003. , pp. 257-264. (doi:10.1109/DFTVS.2003.1250120).

Cazeaux, Jose' Manuel, Rossi, Daniele and Metra, Cecilia (2004) New high speed CMOS self-checking voter At 10th IEEE International On-Line Testing Symposium (IOLTS 2004). Proceedings, Portugal. 12 Jul 2004 - 14 Jul 2014 . , pp. 58-63. (doi:10.1109/OLT.2004.1319660).

Rossi, Daniele, Muccio, Andrea, Nieuwland, Andre, Katoch, Atul and Metra, Cecilia (2004) Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems [error correcting codes] At 10th IEEE International On-Line Testing Symposium (IOLTS 2004). Proceedings, Portugal. 11 - 14 Jul 2004. , pp. 135-140.

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2004) Fast and low-cost clock deskew buffer At 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2004). Proceedings, France. 10 - 13 Oct 2004. , pp. 202-210. (doi:10.1109/DFTVS.2004.1347841).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2005) Low cost scheme for on-line clock skew compensation At 23rd IEEE VLSI Test Symposium. Proceedings, United States. 01 - 05 May 2005. , pp. 90-95. (doi:10.1109/VTS.2005.52).

Nieuwland, Andre, Katoch, Atul, Rossi, Daniele and Metra, Cecilia (2005) Coding techniques for low switching noise in fault tolerant busses At 11th IEEE International On-Line Testing Symposium, France. 06 - 08 Jul 2005. , pp. 183-189. (doi:10.1109/IOLTS.2005.19).

Cazeaux, Jose Manuel, Rossi, Daniele, Omana, Martin, Chatterjee, Abhijit and Metra, Cecilia (2005) On-transistor level gate sizing for increased robustness to transient faults At 11th IEEE International On-Line Testing Symposium (IOLTS 2005), France. 06 - 08 Jul 2005. , pp. 23-28. (doi:10.1109/IOLTS.2005.49).

Metra, Cecilia, Omana, Martin, Rossi, Daniele, Cazeaux, Jose' Manuel and Mak, T.M. (2005) The other side of the timing equation: a result of clock faults At 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), United States. 03 - 05 Oct 2005. , pp. 169-177. (doi:10.1109/DFTVS.2005.65).

Rossi, Daniele, Omana, Martin, Toma, Fabio and Metra, Cecilia (2005) Multiple transient faults in logic: an issue for next generation ICs? At 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), United States. 03 - 05 Oct 2005. , pp. 352-360. (doi:10.1109/DFTVS.2005.47).

Omana, Martin, Cazeaux, Jose Manuel, Rossi, Daniele and Metra, Cecilia (2006) Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects At Design, Automation and Test in Europe (DATE '06). Proceedings, Germany. 06 - 10 Mar 2006. , pp. 170-175. (doi:10.1109/DATE.2006.244061).

Rossi, Daniele, Steiner, Carlo and Metra, Cecilia (2006) Analysis of the impact of bus implemented EDCs on on-chip SSN At Design, Automation and Test in Europe (DATE '06). Proceedings. Volume 1, Germany. 06 - 10 Mar 2006. , pp. 59-64. (doi:10.1109/DATE.2006.243982).

Metra, Cecilia, Rossi, Daniele, Omana, Martin and Cazeaux, Jose' Manuel (2006) Can clock faults be detected through functional test? At 2006 IEEE Design & Diagnostics in Electronic Circuits and Systems, Czech Republic. 18 - 21 Apr 2006. , pp. 168-171. (doi:10.1109/DDECS.2006.1649606).

Metra, Cecilia, Omana, Martin, Rossi, Daniele and Cazeaux, Jose Manuel (2006) Path (min) delay faults and their impact on self-checking circuits’ operation At 12th IEEE International On-Line Testing Symposium, 2006. IOLTS 2006, Italy. , pp. 17-22. (doi:10.1109/IOLTS.2006.47).

Rossi, Daniele, Omana, Martin, Metra, Cecilia and Pagni, Andrea (2006) Checker no-harm alarm robustness At 12th IEEE International On-Line Testing Symposium (IOLTS 2006), Italy. 10 - 12 Jul 2006. , pp. 275-280. (doi:10.1109/IOLTS.2006.16).

Rossi, Daniele, Cazeaux, Jose' Manuel, Metra, Cecilia and Lombardi, Fabrizio (2006) A novel dual-walled CNT bus architecture with reduced cross-coupling features At Sixth IEEE Conference on Nanotechnology (IEEE-NANO 2006), United States. 17 - 20 Jun 2006. , pp. 258-261. (doi:10.1109/NANO.2006.247623).

Rossi, Daniele, Angelini, Paolo and Metra, Cecilia (2007) Configurable error control scheme for NoC signal integrity At 13th IEEE International On-Line Testing Symposium, Greece. 08 - 11 Jul 2007. , pp. 43-48. (doi:10.1109/IOLTS.2007.24).

Metra, Cecilia, Rossi, Daniele, Omana, Martin, Jas, Abhijit and Galivanche, Rajesh (2008) Function-inherent code checking: a new low cost on-line testing approach for high performance microprocessor control logic At IEEE European Test Symposium, Italy. 25 - 29 May 2008. , pp. 171-176. (doi:10.1109/ETS.2008.24).

Rossi, Daniele, Angelini, Paolo, Metra, Cecilia, Campardo, Giovanni and Vanalli, G. P. (2008) Risks for signal integrity in system in package and possible rmedies At IEEE European Test Symposium, Italy. 25 - 29 May 2008. , pp. 165-170. (doi:10.1109/ETS.2008.23).

Ma, X., Huang, F., Chiminazzo, Federica, Rossi, Daniele, Metra, Cecilia and Lombardi, Fabrizio (2008) Resistive crossbar switching networks for inherently fault tolerant nano LUTs At 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, United States. 29 - 30 Sep 2008. , pp. 21-24. (doi:10.1109/NDCS.2008.21).

Omana, Martin, Rossi, Daniele and Metra, Cecilia (2009) Novel high speed robust latch At 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, United States. 07 - 09 Oct 2009. , pp. 65-73. (doi:10.1109/DFT.2009.40).

Omana, Martin, Rossi, Daniele, Bosio, Nicolo' and Metra, Cecilia (2010) Novel low-cost aging sensor At CF '10 Proceedings of the 7th ACM international conference on Computing frontiers, Italy. 17 - 19 May 2010. , pp. 93-94. (doi:10.1145/1787275.1787299).

Rossi, Daniele, Omana, Martin, Berghella, Gianluca, Metra, Cecilia, Chandra, Tirumurti and Galivanche, Rajesh (2010) Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors At ACM International Conference on Computing Frontiers, Italy. 17 - 19 May 2010. , pp. 113-114.

Omana, Martin, Rossi, Daniele, Bosio, Nicolo' and Metra, Cecilia (2010) Self-checking monitor for NBTI due degradation At IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, France. 07 - 09 Jun 2010. , pp. 1-6. (doi:10.1109/IMS3TW.2010.5503006).

Rossi, Daniele, Omana, Martin, Giaffreda, Daniele and Metra, Cecilia (2010) Secure communication protocol for wireless sensor networks At 8th IEEE East-West Design & Test Symposium (EWDTS), Russian Federation. 17 - 20 Sep 2010. , pp. 17-20. (doi:10.1109/EWDTS.2010.5742155).

Rossi, Daniele, Omana, Martin and Metra, Cecilia (2010) Transient fault and soft error on-die monitoring scheme At 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Japan. 06 - 08 Oct 2010. , pp. 391-398. (doi:10.1109/DFT.2010.53).

Rossi, Daniele, Timoncini, Nicola, Spica, Michael and Metra, Cecilia (2011) Error correcting code analysis for cache memory high reliability and performance At IEEE/ACM Design, Automation and Test in Europe (DATE), France. 14 - 18 Mar 2011. , pp. 1-6. (doi:10.1109/DATE.2011.5763257).

Giaffreda, Daniele, Omana, Martin, Rossi, Daniele and Metra, Cecilia (2011) Model for thermal behavior of shaded PV cells under hot-spot condition At IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Canada. 03 - 05 Oct 2011. , pp. 252-258. (doi:10.1109/DFT.2011.47).

Rossi, Daniele, Omana, Martin, Metra, Cecilia and Paccagnella, Alessandro (2011) Impact of aging phenomena on soft error susceptibility At IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Canada. 03 - 05 Oct 2011. , pp. 18-24. (doi:10.1109/DFT.2011.45).

Omana, Martin, Rossi, Daniele, Collepalumbo, Giacomo, Metra, Cecilia and Lombardi, Fabrizio (2012) Faults affecting the control blocks of PV arrays and techniques for their concurrent detection At IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, United States. 03 - 05 Oct 2012. , pp. 199-204. (doi:10.1109/DFT.2012.6378224).

Bolchini, C., Miele, A., Sandionigi, C., Ottavi, M., Pontarelli, S., Salsano, A, Metra, C., Omana, M., Rossi, D., Sonza Reorda, M., Sterpone, L., Violante, M., Gerardin, S., Bagattin, M. and Paccagnella, A. (2012) High-reliability fault tolerant digital systems in nanometric technologies: characterization and design methodologies At IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, United States. 03 - 05 Oct 2012. , pp. 121-125. (doi:10.1109/DFT.2012.6378211).

Omana, Martin, Rossi, Daniele, Fuzzi, Filippo, Metra, Cecilia, Tirumurti, Chandra and Galivanche, Rajesh (2013) Novel approach to reduce power droop during scan-based logic BIST At 18th IEEE European Test Symposium (ETS), France. 27 - 30 May 2013. , pp. 1-6. (doi:10.1109/ETS.2013.6569375).

Rossi, Daniele, Tenentes, Vasileios, Khursheed, Saqib and Al-Hashimi, Bashir (2015) NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating At IEEE European Test Symposium 2015, Romania. 25 - 29 May 2015.

Rossi, Daniele, Tenentes, Vasileios, Khursheed, Saqib and Al-Hashimi, Bashir M. (2015) BTI and leakage aware dynamic voltage scaling for reliable low power cache memories At 21st IEEE International On-Line Testing Symposium, Greece. 06 - 08 Jul 2015. 6 pp.

Tenentes, Vasileios, Rossi, Daniele, Khursheed, Saqib and Al-Hashimi, Bashir M. (2015) Diagnosis of power switches with power-distribution-network consideration At 20th IEEE European Test Symposium (ETS 2015), Romania. 25 - 29 May 2015. 6 pp.

Omana, Martin, Rossi, Daniele, Beniamino, Edda, Metra, Cecilia, Tirumurti, Chandra and Galivanche, Rajesh (2014) Power droop reduction during Launch-On-Shift scan-based logic BIST At 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Netherlands. 01 - 03 Oct 2014. 6 pp, pp. 21-26. (doi:10.1109/DFT.2014.6962063).

Tenentes, Vasileios, Khursheed, Saqib, Rossi, Daniele, Yang, Sheng and Al-Hashimi, Bashir M. (2015) DFT architecture with power-distribution-network consideration for delay-based power gating test IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-12. (doi:10.1109/TCAD.2015.2446939).

Rossi, Daniele, Tenentes, Vasileios, Yang, Sheng, Khursheed, Saqib and Al-Hashimi, Bashir (2015) Reliable power gating with NBTI aging benefits IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-10.

Rossi, Daniele, Tenentes, Vasileios, Yang, Sheng, Khursheed, Saqib and Al-Hashimi, Bashir (2016) Aging benefits in nanometer CMOS designs IEEE Transactions on Circuits and Systems II Express Briefs, pp. 1-5.

Omana, Martin, Rossi, Daniele, Edara, TusharaSandeep and Metra, Cecilia (2016) Impact of aging phenomena on Latches’ robustness IEEE Transactions on Nanotechnology, 15, (2), pp. 129-136. (doi:10.1109/TNANO.2015.2494612).

Omana, Martin, Rossi, Daniele, Beniamino, Edda, Metra, Cecilia, Tirumurti, Chandrasekharan and Galivanche, Rajesh (2015) Low-cost and high-reduction approaches for power droop during launch-on-shift scan-based logic BIST IEEE Transactions on Computers, pp. 1-12. (doi:10.1109/TC.2015.2490058).

Halak, Basel, Rossi, Daniele and Jiajing, Cai (2016) Analysis of BTI aging of level shifters At 22nd IEEE International Symposium on On-Line Testing and Robust System Design.

Chahal, Hardeep, Tenentes, Vasileios, Rossi, Daniele and Al-Hashimi, Bashir M. (2016) BTI aware thermal management for reliable DVFS designs At Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium (DFT'16), United States. 19 - 20 Sep 2016. 6 pp.

Tenentes, Vasileios, Rossi, Daniele, Yang, Sheng, Khursheed, Saqib, Al-Hashimi, Bashir M. and Gunn, Steve R. (2016) Coarse-grained online monitoring of BTI aging by reusing power gating infrastructure IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-12.

Tenentes, Vasileios, Rossi, Daniele, Yang, S, Khursheed, Saqib, Al-Hashimi, Bashir and Gunn, Stephen (2016) Data-set supporting the article entitled "Coarse-grained Online Monitoring of BTI Aging by Reusing Power Gating Infrastructure" University of Southampton doi:10.5258/SOTON/402489 [Dataset]

Halak, Basel, Tenentes, Vasileios and Rossi, Daniele (2016) The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology Microelectronics Reliability, 67, pp. 74-81. (doi:10.1016/j.microrel.2016.10.018).

Halak, Basel, Tenentes, Vasileios and Rossi, Daniele (2016) Data-set supporting the article entitled "The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology" University of Southampton doi:10.5258/SOTON/403411 [Dataset]

Gutierrez Alcala, Mauricio, Daniel, Tenentes, Vasileios, Rossi, Daniele and Kazmierski, Tomasz (2017) Low power probabilistic online monitoring of systematic erroneous behaviour At IEEE European Test Symposium, Limassol, Cyprus. 22 - 26 May 2017. 2 pp.

Gutierrez Alcala, Mauricio, Daniel, Tenentes, Vasileios, Rossi, Daniele and Kazmierski, Tomasz (2017) Susceptible workload evaluation and protection using selective fault tolerance Journal of Electronic Testing, Theory and Applications (JETTA)

Tenentes, Vasileios, Rossi, Daniele, Khursheed, Saqib, Al-Hashimi, Bashir and Chakrabarty, Krishnendu (2017) Dataset for: Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs University of Southampton doi:10.5258/SOTON/D0189 [Dataset]

Rossi, Daniele, Tenentes, Vasileios, Reddy, Sudhakar and Al-Hashimi, Bashir (2017) Exploiting aging benefits for the design of reliable drowsy cache memories IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Tenentes, Vasileios, Rossi, Daniele, Khursheed, Saqib, Al-Hashimi, Bashir and Chakrabarty, Krishnendu (2017) Leakage current analysis for diagnosis of bridge defects in power-gating designs IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (doi:10.1109/TCAD.2017.2729462).

Gutierrez Alcala, Mauricio, Daniel, Tenentes, Vasileios, Kazmierski, Tomasz and Rossi, Daniele (2017) Low cost error monitoring for improved maintainability of IoT applications At IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. 23 - 25 Oct 2017. 6 pp.

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