Electronics and Computer Science (ECS), University of Southampton

Electronics and Computer Science (ECS)

Dr Tom J Kazmierski

Photograph of Dr Tom J Kazmierski
http://widgets.ecs.soton.ac.uk/image.php?id=person_16&maxw=250&maxh=300&corners=0&edge=1&checksum=95b690aca53173e9d696b59aa819003cPhotograph of Dr Tom J Kazmierski
Dr Tom J Kazmierski

ECS, Faculty of Physical Sciences and Engineering
University of Southampton
Southampton, United Kingdom. SO17 1BJ

Position: Academic staff in Electronics and Electrical Engineering
Extension: 23520
Telephone: Work (Voice): +44 (0)23 8059 3520
Email: tjk@ecs.soton.ac.uk
Homepage: http://users.ecs.soton.ac.uk/tjk/
URI: http://id.ecs.soton.ac.uk/person/16 [browse]

Tom works with:

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Tom J Kazmierski received the M.S. degree in Electronic Engineering from the Warsaw University of Technology, Warsaw, Poland, in 1973 and the Ph.D. degree from the Military University of Technology, Warsaw, in 1976.  Currently he is a Senior Lecturer in the School of Electronics and Computer Science, University of Southampton, Southampton, U.K., where he pursues research into numerical modelling, simulation, and synthesis techniques for computer-aided design of very large scale integration (VLSI) circuits and mixed-technology systems. From 1989 to 1990 he was a Lecturer in Microelectronics at the Griffith University in Brisbane, Australia. From 1990 to 1991 Tom worked as a Visiting Research Scientist at the IBM VLSI Technology Division, San Jose, CA, USA where he developed and patented synchronisation techniques for multi-solver simulation backplanes. He has contributed to the development of the VHDL-AMS standard by the IEEE, served as Chair of the IEEE DASC P1076.1 (VHDL-AMS) Working Group from 1999 to 2005. He has published over 140 papers, edited two books, and given a number of invited talks and tutorials mostly in the area of analogue and mixed signal synthesis and hardware description languages. In recent years he has been working on simulation techniques, applications of VHDL-AMS and other hardware description languages to high-level system modelling and synthesis, including automated analogue and mixed-signal synthesis for ASIC design, synthesis of artificial VLSI neural networks, performance modelling of mixed-technology electromechanical systems and energy-harvester powered sensor nodes.

Other Professional Activities

External Examiner at the John Moores University in Liverpool.

Visiting Professor at the Technical University of Vienna.

General Chair for Forum For Design Languages, FDL'10.

General Chair for Virtual Forum for Electronic Design Automation, VW-FEDA'11.

Member of the Technical Programme Committees for DATE, FDL and WUPS.

Member of the IEEE Design Automation Standards Committee.

Member of the DATE Executive Committee

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