EDA Grid
(this project has ended)

With the rapid increase in the density of transistors for IC design and the integration of analogue and mixed signal elements into single chip SoC, it is being ever more necessary to utilise computing power to establish the integrity and reliability of IC designs prior to manufacture.

Unfortunately this mandates the use of compute intensive processes such as statistical simulation (Monte Carlo), fault simulation and optimisation.

One method for the improvement of the speed of design is to leverage computing farms to expadite these simulations and this project is primarily to develop and optimise an EDA GRID (High Performance Computing Array) specifically for this purpose.

The programme of work will investigate load-balancing techniques, simulation management and analysis, modeling and simulation techniques and post-processing techniques.

Type: Potential Postgraduate Project - A suggested project not yet in existance.
Research Groups: Electronic Systems and Devices Group, Electronics and Electrical Engineering
Theme: Design, Automation, Simulation and Optimisation
Dates: 1st October 2005 to 1st October 2008

Partners

• Cadence Design Systems, UK

Principal Investigators

• Dr Peter R Wilson