The University of Southampton

Feasibility of Novel Deca-Nanometer Vertical MOSFETs for Low-cost Radio Frequency Circuit Application

Date:
2007-2010
Theme:
Nanoelectronics
Funding:
EPSRC

This research aims to investigate the use of CMOS-compatible vertical MOSFETs for the implementation of medium-power RF circuits, opening the way to higher integration of RF systems. Vertical transistors are currently of interest because they offer an alternative route to ultra-short channel MOS transistors with relaxed lithography requirements (and hence considerably lower costs), decouple gate length from the packing density and provide improved current drive per unit silicon area compared with conventional lateral CMOS. In this research approaches will be investigated that deliver these benefits through the integration of vertical MOSFETs in a mature CMOS technology with minimum additional masks above those required for standard 0.5 micron CMOS. The intention is to appraise in depth, the feasibility of this novel technology for the manufacture of low-cost RF solutions.

The challenges of vertical MOSFETs for RF applications are high overlap capacitance, short channel effects, susceptibility to dry etch damage and the lack of an appropriate silicidation technology. A detail investigation has been done to deliver solutions for challenges like overlap capacitance, short channel effects and dry etch damage. CMOS compatible Fillet Local Oxidation (FILOX) process, novel structures (frame gate) and optimised process have been researched to reduce the overlap capacitance and to eliminate dry etch damage associated device degradation. The resulting transistors are found to have significantly improved immunity to short channel effects, with near ideal sub-threshold slopes of 70 to 80 mV/decade, and DIBL of 30 to 35 mV/V. Most recently we have developed for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78mV/decade and a DIBL of 30 mV/V. For an 80 nm channel length, a 43% improvement in the drive current is obtained. Vertical transistors with our FILOX process and silicidation resulted in a transistor with low overlap capacitance and high transistor transconductance. While conventional planar nMOS devices exhibit a fT of 10 GHZ in a 0.5 micron technology node, our vertical nMOS devices fabricated by above mentioned FILOX and silicidation process demonstrating a fT of 20 GHZ in the same technology node. We are currently investigating several RF circuits with verical nMOS devices aimed at the highly lucrative 1-10 GHz market.

Primary investigators

  • Peter Ashburn
  • Steve Hall
  • Bill Redman-White
  • Octavian Buiu

Secondary investigator

  • Mohammad Al Hakim

Partner

  • University of Liverpool

Associated research groups

  • Nano Research Group
  • Southampton Nanofabrication Centre
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