The University of Southampton

Low temperature seeded crystallization of amorphous Si for transistor-in-Grain technology


The continued scaling of MOSFETs to the deca-nanometre regime has reached the point where the transistor size is now comparable with the grain size in a polysilicon film (typically 100-200nm). The time is therefore right to research processing techniques that would allow a transistor to be fabricated inside a grain of polysilicon. Such transistors would be expected to have significantly better performance than thin film transistors (TFTs) because grain boundaries would be eliminated from the channel region. The transistor performance might also approach that achievable in single-crystal silicon if good control could be obtained over the quality of the silicon inside the polysilicon grain. The applications for transistor-in-a-grain technology would potentially be enormous, and would include high-performance large area electronics, displays and any technology where low temperature processing was required. In the longer term, this technology may also be attractive for post-scaling CMOS, since it would enable 3D CMOS technologies to be implemented.

Layers of polycrystalline silicon self-assemble during growth and hence the positions of the grains and grain boundaries are random. The key issue in researching transistor-in-a-grain technology is therefore to devise processing techniques that allow the polysilicon grains to be precisely located with respect to the position of the transistor. This thesis investigates grain localization techniques and transistor architectures for transistor-in-grain technology. Two novel methods of low temperature crystallization of amorphous silicon are researched to increase the grain size and controlling the grain boundary locations. One method uses fluorine during metal induced lateral crystallization (MILC) of α-Si, which suppresses random grain nucleation during crystallization anneal and increases the laterally crystallized distance. Fluorine implantation also significantly reduces the density of the nickel-silicide precipitates and improves the grain texture in the laterally crystallized silicon. Another method employs germanium seed where a new amorphous silicon crystallization phenomenon has been identified to originate from the perimeter of the germanium seed during low temperature anneal and grain localization is achieved without any metal contamination. These methods of devising high quality poly-silicon layer have considerable commercial potential for a number of devices like thin film transistors for large area electronics, transistor-in-grain for 3D CMOS, thin film solar cells, sensor applications in a cost effective thin film based nanowire technology and any devices where low temperature processing is required.

Primary investigator

  • Peter Ashburn

Secondary investigator

  • Mohammad Al Hakim

Associated research groups

  • Nano Research Group
  • Southampton Nanofabrication Centre
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