The UK Research Programme concerned with developing SiGe MOS technologies.
Funded pricipally by the EPSRC, 13 research teams from 9 UK universities work together on the programme along with industrial partners Avant!, Daimler- Chrysler, Infineon Technologies and Zarlink Semiconductor.
The project is concerned with the integration of strained silicon and silicon germanium layers in decananometre CMOS processes, with both conventional doped polysilicon gate and metal replacement gate processes. Work is also focused on limited area growth SiGe for virtual substrate strained silicon devices and the integration of a high-k gate dielectric into a SiGe MOS process. Homepage: http://www.sigemos.com
Type: Normal Research Project
Research Group: Nano Research Group
Themes: Silicon Electronic Devices, Nanomaterials and Dielectrics
Dates: 1st September 2000 to 1st September 2003
Partners- University of Warwick
- University of Cambridge
- Imperial College
- University of Sheffield
- University of Newcastle Upon Tyne
- Loughborough University
- University of Glasgow
- UMIST
- Infineon Technologies
- Daimler- Chrysler
- Zarlink Semiconductor
- Avant!
FundingPrincipal InvestigatorsOther Investigators | 
