Over the past 20 years, the channel length of MOS transistors has halved at intervals of
approximately every two or three years, which has led to a virtuous circle of increasing packing
density (more complex electronic products), increasing performance (higher clock
frequencies) and decreasing costs per unit silicon area. To continue on this path,
Research is underway at Southampton University to investigate an alternative method of fabricating
short-channel MOS transistors, socalled Vertical MOSFET's. In these devices the channel is
perpendicular to the wafer surface in stead of in the plane of the surface.
Vetical MOSFET's have three main advantages:
First, the channel length of the vertical MOS transistor is not defined by lithography.
This means no requirements for post-optical lithography techniques such as x-ray, extreme
ultra-violet, electron projection lithography, ion projection lithography or
direct write e-beam which are possibly prohibitively expensive.
Second, Vertical MOS transistors are easily made with both front gate and back gate.
Using this technology doubles the channel width per transistor area. Combined with easier design
rules, this leads to an increase of packing density of at least a factor of four as compared
to horizontal transitors.
One step further, is the use of very narrow pillars with the gate surrounding the entire pillar.
This way, fully depleted transistors can be produced which have all the advantages of SOI transistors.
Third advantage of the vertical MOSFET is the possibility to prevent short channel effects from
dominating the transitor by adding processes that are not easily realised in horizontal
transistors, such as a polysilicon (or polySiGe) source to reduce parasitic bipolar effects
or a dielectric pocket to reduce drain induced barrier lowering (dibl).