The University of Southampton
Email:
s.maheshwari@soton.ac.uk

Dr Sachin Maheshwari PhD

Research Fellow

Sachin Maheshwari is a Research Fellow at the Centre for Electronics Frontiers in the Zepler Institute at the University of Southampton. He did his Ph.D. in the Applied DSP and VLSI Research Group at the University of Westminster, London, UK. His doctoral thesis was focussed on the Adiabatic Approach for Low-Power Passive NFC systems. He has a Master's Degree in Microelectronics from Birla Institute of Technology and Science (BITS), Pilani, India, and a Bachelor's Degree in Electrical and Electronics Engineering from ICFAI Tech, India. In the past, he was also a Lecturer in the EEE Department at BITS Pilani for over 4 years.

Research

Research interests

His current research interests include the Design of Energy and Area Efficient Integrated Circuit Design and Energy Recovery Logic.

Publications

Wang, Jiaqi, Serb, Alexantrou, Papavassiliou, Christos, Maheshwari, Sachin and Prodromakis, Themistoklis (2021) Analysing and measuring the performance of memristive integrating amplifiers. International Journal of Circuit Theory and Applications, 49 (11), 1-19. (doi:10.1002/cta.3101).

Maheshwari, Sachin, Stathopoulos, Spyros, Wang, Jiaqi, Serb, Alexantrou, Pan, Yihan, Mifsud, Andrea, Leene, Lieuwe, Shen, Jiawei, Papavassiliou, Christos, Constandinou, Timothy and Prodromakis, Themistoklis (2021) Design flow for hybrid CMOS/memristor systems-part I: modelling and verification steps. IEEE Transactions on Circuits and Systems I: Regular Papers, 68 (12), 4862-4875. (doi:10.1109/TCSI.2021.3122343).

Maheshwari, Sachin, Stathopoulos, Spyros, Wang, Jiaqi, Serb, Alexantrou, Pan, Yihan, Mifsud, Andrea, Leene, Lieuwe, Shen, Jiawei, Papavassiliou, Christos, Constandinou, Timothy and Prodromakis, Themistoklis (2021) Design flow for hybrid CMOS/memristor systems part II: circuit schematics and layout. IEEE Transactions on Circuits and Systems I: Regular Papers. (doi:10.1109/TCSI.2021.3122381).

Maheshwari, Sachin and Kale, Izzet (2019) Impact of adiabatic logic families on the power-clock generator energy efficiency. In 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME). pp. 25-28 .

Maheshwari, Sachin, Bartlett, Viv and Kale, Izzet (2019) Modelling, simulation and verification of 4-phase adiabatic logic design: a VHDL-based approach. Integration the VLSI Journal, 67, 144-154. (doi:10.1016/j.vlsi.2019.01.007).

Maheshwari, Sachin, Serb, Alexantrou, Papavassiliou, Christos and Prodromakis, Themistoklis (2021) An adiabatic regenerative capacitive artificial neuron. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. vol. 2021-May, IEEE. pp. 1-5 . (doi:10.1109/ISCAS51556.2021.9401142).

Contact

Share this profile FacebookTwitterWeibo