The University of Southampton

Dr Terrence Mak

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Terrence Mak is an Associate Professor at Electronics and Computer Science, University of Southampton. Supported by the Royal Society, he was a Visiting Scientist at Massachusetts Institute of Technology during 2010, and also, affiliated with the Chinese Academy of Sciences as a Visiting Professor since 2013. Previously, He worked with Turing Award holder Prof. Ivan Sutherland, at Sun Lab in California and has awarded Croucher Foundation scholar. His newly proposed approaches, using runtime optimization and adaptation, strengthened network reliability, reduced power dissipations and significantly improved overall on-chip communication performances. Throughout a spectrum of novel methodologies, including traffic dynamics using network-on-chips, enabling unprecedented MTBF and to provide better on-chip efficiencies, and proposed a novel garbage collections methods, “defragmentation”, together led to four prestigious best paper awards at DATE 2011, IEEE/ACM VLSI-SoC 2014, IEEE PDP 2015, and IEEE EUC 2016. More recently, his newly published journal based on 3D adaptation and deadlock-free routing has awarded the prestigious 2015 IET Computers & Digital Techniques Premium Award. He has published more than 120 papers in both conferences and journals and jointly published 4 books.  



Research interests

3D-IC design, computer architecture design, FPGA design, network-on-chips (NoC), on-chip power management


Dehir, Nizar, Mak, Terrence, Fei, Xia and Alex, Yakovlev (2012) Modeling and tools for power supply variations analysis in networks-on-chip. IEEE Transactions on Computers, 63 (3), 679-690. (doi:10.1109/TC.2012.272).

Tarawneh, Gareth, Yakovlev, Alex and Mak, Terrence (2014) Eliminating synchronization latency using sequenced latching. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22 (2), 408-419. (doi:10.1109/TVLSI.2013.2243177).

Dahir, Nizar, Al-Dujaily, Ra'ed, Mak, Terrence and Yakovlev, Alex (2014) Thermal optimization in network-on-chip-based 3D chip multiprocessors using dynamic programming networks. [in special issue: Real-Time and Embedded Technology and Applications, Domain-Specific Multicore Computing, Cross-Layer Dependable Embedded Systems, and Application of Concurrency to System Design (ACSD'13)] ACM Transactions on Embedded Computing Systems, 13 (4s), 1-25. (doi:10.1145/2584668).

AL-DUJAILY, RAAED, Li, An, Maunder, Robert, Mak, Terrence, Al-Hashimi, Bashir and Hanzo, Lajos (2016) A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation. University of Southampton [Dataset]

Karkar, Ammar, Mak, Terrence, Tong, Kin-Fai and Yakolev, Alex (2016) A survey of emerging interconnects for on-chip efficient multicast and broadcast in many-cores. IEEE Circuits and Systems Magazine, 16 (1), 58-72.

Opoku Agyeman, M., Vien, Q., Yakovlev, A., Tong, K. and Mak, T. (2017) A resilient 2-D waveguide communication fabric for hybrid wired-wireless NoC design. IEEE Transactions on Parallel and Distributed Systems, 1-14. (doi:10.1109/TPDS.2016.2575836).

Karkar, A., Mak, T., Tong, K. and Yakovlev, A. (2016) Network-on-chip multicast architectures using hybrid wire and surface-wave interconnects. IEEE Transaction on Emerging Topics in Computing, 1-12. (doi:10.1109/TETC.2016.2551043).

Ng, J., Singh, A., Wang, X. and Mak, T. (2016) Defragmentation for efficient runtime resource management in NoC-based many-core systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24 (11), 3359-3372. (doi:10.1109/TVLSI.2016.2548564).

Wang, X., Zhao, B., Wang, L., Mak, T., Yang, M. and Daneshtalab, M. (2016) A pareto-optimal runtime power budgeting scheme for many-core systems. Microprocessors and Microsystems, 46, part B, 136-148.

Fei, T., Wang, X., Zhang, B. and Mak, T. (2016) On runtime adaptive tile defragmentation for resource management in many-core systems. Microprocessors and Microsystems, 46, part B, 161-174. (doi:10.1016/j.micpro.2016.02.004).

Wang, X., Zhao, B., Mak, T., Yang, M., Jiang, Y. and Daneshtalab, M. (2016) On fine-grained runtime power budgeting for networks-on-chip systems. IEEE Transactions on Computers, 65 (9), 2780-2793.

Liu, Q., Ji, W., Chen, Q. and Mak, T. (2016) IP protection of mesh NoCs using square spiral routing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24 (4), 1560-1573.

Agyeman, M., Tong, K. and Mak, T. (2015) An improved wireless communication fabric for emerging Network-on-Chip design. [in special issue: The 10th International Conference on Future Networks and Communications (FNC 2015) / The 12th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2015) Affiliated Workshops] Procedia Computer Science, 56, 415-420.

Yi, W., Lo, K., Mak, T., Leung, K., Leung, Y. and Meng, H. (2015) A survey of wireless sensor network based air pollution monitoring systems. Sensors, 15 (12), 31392-31427.

Wang, X., Zhao, B., Mak, T., Yang, M. and Daneshtalab, M. (2015) An efficient runtime power allocation scheme for many-core systems inspired from auction theory. Integration the VLSI Journal, 50, 147-157. (doi:10.1016/j.vlsi.2014.11.001).

Luo, R., Coapes, G., Mak, T., Tadashi, Y., Degena, P. and Tin, C. (2016) Real-time simulation of passage-of-time encoding in cerebellum using a scalable FPGA-based system. IEEE Transactions on Biomedical Circuits and Systems, 10 (3), 742-753. (doi:10.1109/TBCAS.2015.2460232). (PMID:26452290)

Al-Dujaily, Ra'ed, Li, An, Maunder, Robert G, Mak, Terrence, Al-Hashimi, Bashir M. and Hanzo, Lajos (2016) A scalable turbo decoding algorithm for high-throughput network-on-chip implementation. IEEE Access, 1-1. (doi:10.1109/ACCESS.2016.2628801).

Wang, Xiaohang, Singh, Amit, Li, Bing, Yang, Yang, Li, Hong and Mak, Terrence (2018) Bubble budgeting: throughput optimization for dynamic workloads by exploiting dark cores in many core systems. IEEE Transactions on Computers, 67 (2), 178-192. (doi:10.1109/TC.2017.2735967).

Fletcher, Benjamin, James, Das, Shidhartha and Mak, Terrence (2017) Dataset supporting the paper entitled “A High-Speed Design Methodology for Inductive Coupling Links in 3D-ICs”. University of Southampton doi:10.5258/SOTON/D0312 [Dataset]

Fletcher, Benjamin, James, Das, Shidhartha, Poon, Chi-Sang and Mak, Terrence (2017) Dataset supporting the paper entitled “Low-Power 3D Integration using Inductive Coupling Links for Neurotechnology Applications". University of Southampton doi:10.5258/SOTON/D0318 [Dataset]

Wang, Ling and Mak, Terrence (2018) A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip. Journal of Circuits, Systems and Computers, 27 (2). (doi:10.1142/S0218126618500226).

Fletcher, Benjamin James, Das, Shidhartha and Mak, Terrence (2017) A high-speed design methodology for inductive coupling links in 3D-ICs. Design Automation and Test in Europe, Dresden, Germany. 19 - 23 Mar 2018. 6 pp. (In Press)

Fletcher, Benjamin James, Das, Shidhartha, Poon, Chi-Sang and Mak, Terrence (2018) Low-power 3D integration using inductive coupling links for neurotechnology applications. Design Automation and Test in Europe, Dresden, Germany. 19 - 23 Mar 2018. 6 pp.

Wang, Liang, Wang, Xiaohang, Leung, Ho Fung and Mak, Terrence (2018) Runtime task mapping for lifetime budgeting in many-core systems. In FDL 2017 - Proceedings of the 2017 Forum on Specification and Design Languages. vol. 2017-September, IEEE Computer Society. 8 pp, pp. 1-8. (doi:10.1109/FDL.2017.8303900).


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