Over the past few years SiGe heterojunction bipolar transistors have come out of the research laboratory and gone into production in BiCMOS processes around the world. The state of the art fT and fmax are around 200GHz, which is ideal for rf circuit applications up to 20GHz and optical communications applications up to 40Gbit/s.
To date, all SiGe HBTs have been produced with a vertical architecture in which the emitter is placed above the base and the base above the collector. Although this approach has given the above impressive performance, it has a number of disadvantages. These disadvantages arise from the need to make a contact to the collector, which is buried below the surface. A heavily doped buried layer is needed beneath the collector to reduce the collector resistance, and epitaxy has to be used to create the lower doped collector on top of the buried layer. Epitaxy is a very expensive process, and even with a very heavily doped buried layer, it is not possible to achieve very low values of collector resistance.
In principle, this problem could be solved by using a lateral architecture in which the emitter, base and collector were placed side by side at the surface. Contact to the collector could then be made directly from the surface, giving a very low value of collector resistance and eliminating the need for collector epitaxy. This arrangement would also be more compatible with CMOS, where the MOS transistors are fabricated using a lateral architecture. Silicon lateral bipolar transistors have been available for some time, but they tend to be low frequency devices because of the parasitic capacitances associated with them. Lateral SiGe HBTs have never been reported.
To produce a high frequency lateral SiGe HBT, it is necessary to minimise parasitic capacitance and at the same time find a method of producing a lateral SiGe layer. Silicon on insulator (SOI) technology offers one method of reducing parasitic capacitance, and has delivered an extremely impressive fmax of 67GHz on lateral silicon bipolar transistors. Simulations of lateral SiGe HBTs on SOI substrates indicate that the lateral SiGe HBT on SOI outperforms the vertical HBT, especially in terms of fmax. Confined lateral selective epitaxial growth (CLSEG) and germanium implantation are two possible methods of creating a lateral SiGe layer. Both techniques have shown promising results.
In this project, confined lateral selective epitaxial growth is being investigated for the fabrication of lateral devices in growth chambers fabricated on the surface of the silicon wafer. Device design issues are being investigated by process and device simulation.