Event details
We present a design methodology for fault-tolerant ASIC that is based on radiation-hard technology, redundant circuits with latchup protection, additional logic and layout implementation steps, and power gating. Enhancements have been made within the standard ASIC design flow in order to incorporate redundancy and power-switch cells and, consequently, enable protection against single-event upset (SEU), single-event transient (SET), and single-event latchup (SEL). In order to validate the proposed fault-tolerant circuits, a fault-injection environment including fault models has been developed. These techniques are being exploited and implemented in the SEPHY project (http://
www.sephy.eu).
In order to automate a design flow of the fault-tolerant circuits, it is essential to design specific cells which are not present in the standard or radiation-hard design kits. A SEL protection switch (SPS) is described first. It consists of a current sensor/driver, feedback block, control block, and communication interface for a power network controller. Measurement results of the irradiated test circuits with protection switches of different types and sizes will be presented. Afterwards, the details of triple-modular redundant (TMR) and double-modular redundant (DMR) circuits with latchup protection and separated power domains are given. Fault-injection models for TMR and DMR circuits are developed in order to simulate and verify the fault-tolerant designs. Functional simulation of a digital design at the gate level suffices in case of the single-event transient and upset effects. However, in order to provide the information about design behavior during latchup effect, it is required to functionally simulate the design at the transistor level. TMR and DMR circuit simulation results with the implemented fault-injection models for all three types of the mentioned single-event effects will be presented.