The University of Southampton
×
Electronics and Computer Science
Email:
d.b.thomas@soton.ac.uk

Professor David Thomas 

I studied Computer Science as an undergrad at the Dept. of Computing in Imperial,
then did my PhD in digital architectures in the same department. After 5 years as
a researcher associate and then research fellow, in 2010 I moved to the Dept. of Electrical
and Electronic Engineer at Imperial as a Lecturer, then Senior Lecturer. In 2021 I joined
the Electronics and Computer Science Dept. as a Professor. Both my research and teaching
interests are at the intersection of software and hardware, particularly in the interaction and
relationshops between programming languages, algorithms, computer achitecture and digital
implementation. A lot of my research involves the use of FPGAs (Field Programmable Gate
Arrays), as they provide a great playground for exploring and implementing new digital architectures,
such as custom CPUs, application-specific accelerators, or new programming paradigms such
as event-driven computing.

Research

Research interests

My research interests range up and down the hardware-software stack, from low-level implementation
of mathematical digital blocks, through to custom processors and on-chip networks, and up into high-level
languages for describing pipelined and distributed programs. A lot of my work involves FPGAs, which
are useful both as prototyping platforms and as target computational platforms. I'm particularly interested
in languages and architectural patterns which make it easier to program FPGAs (and other digital architectures),
such as High-Level Synthesis (HLS), meta-programming for logic design, and hardware co-ordination using
events. Some overall research themes include:

  • Financial computing, such as credit-risk analysis and option pricing, using FPGAs and GPUs
  • Highly optimised uniform and non-uniform random number generation for FPGAs, providing best-in-class area-efficiency-quality tradeoffs
  • Meta-programming for high-level synthesis, in order to allow extension of the HLS language and primitives at compile-time
  • Event-driven computing as a way of designing programmes for large multi-FPGA systems

Teaching

Previously I was the course director for the EIE (Electrical and Information Engineering) degree at Imperial College,
which covered both computer science and electrical engineering. I've previously taught and assessed the following subjects:

  • Programming
  • Computer Architecture
  • Compilers
  • Networks
  • Databases
  • High-performance Computing

Publications

Xue, Zeping and Thomas, David B. (2016) SynADT: dynamic data structures in high level synthesis. In Proceedings - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016. Institute of Electrical and Electronics Engineers Inc. pp. 64-71 . (doi:10.1109/FCCM.2016.26).

Todman, Tim, Thomas, David and Luk, Wayne (2021) Exploring performance enhancement of event-driven processor networks. In Proceedings - 2020 International Conference on Field-Programmable Technology, ICFPT 2020. Institute of Electrical and Electronics Engineers Inc. 1 pp . (doi:10.1109/ICFPT51103.2020.00056).

Thomas, David B. (2016) Synthesisable recursion for C++ HLS tools. In 2016 IEEE 27th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2016. vol. 2016-November, Institute of Electrical and Electronics Engineers Inc. pp. 91-98 . (doi:10.1109/ASAP.2016.7760777).

Thomas, David B. (2019) Templatised soft floating-point for high-level synthesis. In Proceedings - 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019. Institute of Electrical and Electronics Engineers Inc. pp. 227-235 . (doi:10.1109/FCCM.2019.00038).

Thomas, David B. (2019) Compile-time generation of custom-precision floating-point IP using HLS tools. Takagi, Naofumi, Boldo, Sylvie and Langhammer, Martin (eds.) In Proceedings - 26th IEEE Symposium on Computer Arithmetic, ARITH 2019. vol. 2019-June, Institute of Electrical and Electronics Engineers Inc. pp. 192-193 . (doi:10.1109/ARITH.2019.00044).

Tavakkoli, Aryan and Thomas, David B. (2017) A high-level design framework for the automatic generation of high-throughput systolic binomial-tree solvers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26 (2), 341-354, [8081850]. (doi:10.1109/TVLSI.2017.2761554).

Tarawneh, Ghaith, Mokhov, Andrey, Naylor, Matthew, Rast, Alex, Moore, Simon W., Thomas, David B., Yakovlev, Alex and Brown, Andrew (2017) Programming model to develop supercomputer combinatorial solvers. In Proceedings - 46th International Conference on Parallel Processing Workshops, ICPPW 2017. Institute of Electrical and Electronics Engineers Inc. pp. 171-179 . (doi:10.1109/ICPPW.2017.35).

Su, Jiang, Fraser, Nicholas J., Gambardella, Giulio, Blott, Michaela, Durelli, Gianluca, Thomas, David B., Leong, Philip H.W. and Cheung, Peter Y.K. (2018) Accuracy to throughput trade-offs for reduced precision neural networks on reconfigurable logic. Voros, Nikolaos, Keramidas, Georgios, Antonopoulos, Christos, Huebner, Michael, Diniz, Pedro C. and Goehringer, Diana (eds.) In Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. vol. 10824 LNCS, Springer-Verlag. pp. 29-42 . (doi:10.1007/978-3-319-78890-6_3).

Su, Jiang, Thomas, David B. and Cheung, Peter Y.K. (2016) Increasing network size and training throughput of FPGA restricted Boltzmann machines using dropout. In Proceedings - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016. Institute of Electrical and Electronics Engineers Inc. pp. 48-51 . (doi:10.1109/FCCM.2016.23).

Li, Qiang, Wang, Erwei, Fleming, Shane T., Thomas, David B. and Cheung, Peter Y.K. (2019) Accelerating position-aware top-k listnet for ranking under custom precision regimes. Sourdis, Ioannis, Bouganis, Christos-Savvas, Alvarez, Carlos, Toledo Diaz, Leonel Antonio, Valero, Pedro and Martorell, Xavier (eds.) In Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. Institute of Electrical and Electronics Engineers Inc. pp. 81-87 . (doi:10.1109/FPL.2019.00022).

Inggs, Gordon, Thomas, David B. and Luk, Wayne (2017) A domain specific approach to high performance heterogeneous computing. IEEE Transactions on Parallel and Distributed Systems, 28 (1), 2-15, [7465804]. (doi:10.1109/TPDS.2016.2563427).

Fleming, Shane T. and Thomas, David B. (2016) StitchUp: Automatic control flow protection for high level synthesis circuits. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. vol. 05-09-June-2016, Institute of Electrical and Electronics Engineers Inc.. (doi:10.1145/2897937.2898097).

Su, Jiang, Faraone, Julian, Liu, Junyi, Zhao, Yiren, Thomas, David B., Leong, Philip H.W. and Cheung, Peter Y.K. (2018) Redundancy-reduced MobileNet acceleration on reconfigurable logic for ImageNet classification. Voros, Nikolaos, Keramidas, Georgios, Antonopoulos, Christos, Huebner, Michael, Diniz, Pedro C. and Goehringer, Diana (eds.) In Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. vol. 10824 LNCS, Springer-Verlag. pp. 16-28 . (doi:10.1007/978-3-319-78890-6_2).

Salem, V., Izzi-Engbeaya, C., Coello, C., Thomas, D. B., Chambers, E. S., Comninos, A. N., Buckley, A., Win, Z., Al-Nahhas, A., Rabiner, E. A., Gunn, R. N., Budge, H., Symonds, M. E., Bloom, S. R., Tan, T. M. and Dhillo, W. S. (2015) Glucagon increases energy expenditure independently of brown adipose tissue activation in humans. Diabetes, Obesity and Metabolism, 18 (1), 72-81. (doi:10.1111/dom.12585).

Naylor, Matthew, Moore, Simon W., Thomas, David, Beaumont, Jonathan R., Fleming, Shane, Vousden, Mark, Markettos, A. Theodore, Bytheway, Thomas and Brown, Andrew (2021) General hardware multicasting for fine-grained message-passing architectures. In Proceedings - 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2021. Institute of Electrical and Electronics Engineers Inc. pp. 126-133 . (doi:10.1109/PDP52278.2021.00028).

Brown, Andrew, Vousden, Mark, Bragg, Graeme McLachlan, Shillcock, Julian, Beaumont, Jonathan and Thomas, David Barrie (2021) Coupling bulk phase separation of disordered proteins to membrane domain formation in molecular simulations on a bespoke compute fabric. Membranes, 12 (1). (doi:10.3390/membranes12010017).

Shahsavari, Mahyar, Beaumont, Jonathan, Thomas, David and Brown, Andrew (2021) POETS: A parallel cluster architecture for Spiking Neural Network. International Journal of Machine Learning and Computing, 11 (4), 281-285. (doi:10.18178/ijmlc.2021.11.4.1048).

Shahsavari, Mahyar, Thomas, David, Brown, Andrew and Luk, Wayne (2021) Neuromorphic design using reward-based STDP learning on event-based reconfigurable cluster architecture. In ICONS 2021 - Proceedings of International Conference on Neuromorphic Systems 2021. The Association for Computing Machinery. 8 pp . (doi:10.1145/3477145.3477151).

Rafiev, Ashur, Morris, Jordan, Xia, Fei, Yakovlev, Alex, Naylor, Matthew, Moore, Simon, Thomas, David, Bragg, Graeme, Vousden, Mark and Brown, Andrew (2022) Practical distributed implementation ofvery large scale petri net simulations. Koutny, Maciej, Kordon, Fabrice and Moldt, Daniel (eds.) In Transactions on Petri Nets and Other Models of Concurrency XVI. vol. 13220 LNCS, Springer Science and Business Media Deutschland GmbH. pp. 112-139 . (doi:10.1007/978-3-662-65303-6_6).

Rafiev, Ashur, Yakovlev, Alex, Tarawneh, Ghaith, Naylor, Matthew F., Moore, Simon W., Thomas, David B., Bragg, Graeme M., Vousden, Mark L. and Brown, Andrew D. (2022) Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. IET Computers and Digital Techniques, 16 (2-3), 71-88. (doi:10.1049/cdt2.12041).

Brown, Andrew, Todman, Tim, Luk, Wayne, Thomas, David, Vousden, Mark, Bragg, Graeme, Beaumont, Jonny, Moore, Simon, Yakovlev, Alex and Rafiev, Ashur (2022) Non-deterministic event brokered computing. In Proceedings of the 12th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2022. The Association for Computing Machinery. pp. 84-86 . (doi:10.1145/3535044.3535055).

Contact

Email: d.b.thomas@soton.ac.uk

Share this profile FacebookTwitterWeibo