Theme:

MEMs and NEMs

Funding:

EP/E043631/1

Atom chips are microfabricated surfaces capable of splitting, guiding and manipulating atoms by application of electric and magnetic fields. Although some basic functionalities were demonstrated earlier, integration of these functions still remains a challenge from microfabrication stand point. The integrated atom chips with stacked layers were prone for misalignment during fabrication. We have therefore micrabricated electrostatic actuators to compensate the misalignments in the stacked layers. The electrostatic actuator structures consists of flexures and trusses to move the optical mirrors in the wafer plane in order to compensate the misalignements if any, besides facilitating to tune the optical cavity for characterising the atoms.

Primary investigators

• ps2
• mk1

Partner

• Blackett Laboratory, Imperial College, London

Associated research groups

• Nano Research Group
• Southampton Nanofabrication Centre

Date:

2003-2007

Theme:

Nanoelectronics

The continued scaling of MOSFETs to the deca-nanometre regime has reached the point where the transistor size is now comparable with the grain size in a polysilicon film (typically 100-200nm). The time is therefore right to research processing techniques that would allow a transistor to be fabricated inside a grain of polysilicon. Such transistors would be expected to have significantly better performance than thin film transistors (TFTs) because grain boundaries would be eliminated from the channel region. The transistor performance might also approach that achievable in single-crystal silicon if good control could be obtained over the quality of the silicon inside the polysilicon grain. The applications for transistor-in-a-grain technology would potentially be enormous, and would include high-performance large area electronics, displays and any technology where low temperature processing was required. In the longer term, this technology may also be attractive for post-scaling CMOS, since it would enable 3D CMOS technologies to be implemented.

Layers of polycrystalline silicon self-assemble during growth and hence the positions of the grains and grain boundaries are random. The key issue in researching transistor-in-a-grain technology is therefore to devise processing techniques that allow the polysilicon grains to be precisely located with respect to the position of the transistor. This research investigates grain localization techniques and transistor architectures for transistor-in-grain technology. Two novel methods of low temperature crystallization of amorphous silicon are researched to increase the grain size and control the grain boundary locations. One method uses fluorine during metal induced lateral crystallization (MILC) of α-Si, which suppresses random grain nucleation during crystallization anneal and increases the laterally crystallized distance. Fluorine implantation also significantly reduces the density of the nickel-silicide precipitates and improves the grain texture in the laterally crystallized silicon. Another method employs a germanium seed and gives crystallization from the perimeter of the germanium seed. This is a new crystallization mechanism that has not been reported previously and has the advantage that crystallization can be achieved without any metal contamination. These methods of devising high quality poly-silicon layer have considerable commercial potential for a number of devices like thin film transistors for large area electronics, transistor-in-grain for 3D CMOS, thin film solar cells, sensor applications in a cost effective thin film based nanowire technology and any devices where low temperature processing is required.

Primary investigator

• pa

Secondary investigator

• mmah

Associated research groups

• Nano Research Group
• Southampton Nanofabrication Centre

Date:

2007-2010

Theme:

Nanoelectronics

Funding:

EPSRC

This research aims to investigate the use of CMOS-compatible vertical MOSFETs for the implementation of medium-power RF circuits, opening the way to higher integration of RF systems. Vertical transistors are currently of interest because they offer an alternative route to ultra-short channel MOS transistors with relaxed lithography requirements (and hence considerably lower costs), decouple gate length from the packing density and provide improved current drive per unit silicon area compared with conventional lateral CMOS. In this research approaches will be investigated that deliver these benefits through the integration of vertical MOSFETs in a mature CMOS technology with minimum additional masks above those required for standard 0.5 micron CMOS. The intention is to appraise in depth, the feasibility of this novel technology for the manufacture of low-cost RF solutions.

The challenges of vertical MOSFETs for RF applications are high overlap capacitance, short channel effects, susceptibility to dry etch damage and the lack of an appropriate silicidation technology. A detail investigation has been done to deliver solutions for challenges like overlap capacitance, short channel effects and dry etch damage. A CMOS compatible Fillet Local Oxidation (FILOX) process has been developed and novel structures (frame gate) proposed to reduce the overlap capacitance and to eliminate dry etch damage associated device degradation. The resulting transistors are found to have significantly improved immunity to short channel effects, with near ideal sub-threshold slopes of 70 to 80 mV/decade, and DIBL of 30 to 35 mV/V. More recently we have developed for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78mV/decade and a DIBL of 30 mV/V. For an 80 nm channel length, a 43% improvement in the drive current is obtained. Vertical transistors with our FILOX process and silicidation resulted in a transistor with low overlap capacitance and high transistor transconductance. While conventional planar nMOS devices exhibit a fT of 10 GHZ in a 0.5 micron technology node, our vertical nMOS devices fabricated by above mentioned FILOX and silicidation process demonstrating a fT of 20 GHZ in the same technology node. We are currently investigating several RF circuits with verical nMOS devices aimed at the highly lucrative 1-10 GHz market.

Primary investigators

• pa
• Steve Hall
• Bill Redman-White
• Octavian Buiu

Secondary investigators

• mmah
• Lizhe Tan

Partner

• University of Liverpool

Associated research groups

• Nano Research Group
• Southampton Nanofabrication Centre

Date:

2007-2009

Themes:

Microfluidics and Lab-on-a-chip, Bio-inspired computing

Living cells are arguably sophisticated unconventional computers equipped with properties difficult to archive with silicon-based computing architectures. However, limited access to (intra)cellular processes is a problem for this novel computing substrate. Although optical interfaces so far have been conventionally adopted as the common method, this often requires bulky setup, such as microscopes, and thus is hard to miniaturise the whole system. We developed an alternative interface device using the electrical impedance spectroscopy (EIS) technique to access the molecular computing processes. The plasmodium of true slime mould, Physaurm polycephalum, is interfaced to the EIS hardware, together with the microfluidic system. This enables a compact monitoring system for the cell's reactions to various external signals. At the talk, we will review our approaches for bio-hybrid devices, robot controller and biosensor, using the electrical interface and the Physarum cell.

Primary investigators

• st07v
• Klaus-Peter Zauner
• Hywel Morgan

Associated research groups

• Science and Engineering of Natural Systems Group
• Nano Research Group