- Date:
- 2001-2007
- Theme:
- Silicon Electronic Devices
- Funding:
- EPSRC
Over the past few years SiGe heterojunction bipolar transistors have come out of the research laboratory and gone into production in BiCMOS processes around the world. The state of the art fT and fmax are around 200GHz, which is ideal for rf circuit applications up to 20GHz and optical communications applications up to 40Gbit/s.
To date, all SiGe HBTs have been produced with a vertical architecture in which the emitter is placed above the base and the base above the collector. Although this approach has given the above impressive performance, it has a number of disadvantages. These disadvantages arise from the need to make a contact to the collector, which is buried below the surface. A heavily doped buried layer is needed beneath the collector to reduce the collector resistance, and epitaxy has to be used to create the lower doped collector on top of the buried layer. Epitaxy is a very expensive process, and even with a very heavily doped buried layer, it is not possible to achieve very low values of collector resistance.
In principle, this problem could be solved by using a lateral architecture in which the emitter, base and collector were placed side by side at the surface. Contact to the collector could then be made directly from the surface, giving a very low value of collector resistance and eliminating the need for collector epitaxy. This arrangement would also be more compatible with CMOS, where the MOS transistors are fabricated using a lateral architecture. Silicon lateral bipolar transistors have been available for some time, but they tend to be low frequency devices because of the parasitic capacitances associated with them. Lateral SiGe HBTs have never been reported.
To produce a high frequency lateral SiGe HBT, it is necessary to minimise parasitic capacitance and at the same time find a method of producing a lateral SiGe layer. Silicon on insulator (SOI) technology offers one method of reducing parasitic capacitance, and has delivered an extremely impressive fmax of 67GHz on lateral silicon bipolar transistors. Simulations of lateral SiGe HBTs on SOI substrates indicate that the lateral SiGe HBT on SOI outperforms the vertical HBT, especially in terms of fmax. Confined lateral selective epitaxial growth (CLSEG) and germanium implantation are two possible methods of creating a lateral SiGe layer. Both techniques have shown promising results.
In this project, confined lateral selective epitaxial growth is being investigated for the fabrication of lateral devices in growth chambers fabricated on the surface of the silicon wafer. Device design issues are being investigated by process and device simulation.
Primary investigators
Associated research group
- Nano Research Group
- Date:
- 2001-2004
- Theme:
- Silicon Electronic Devices
- Funding:
- EPSRC
Bipolar transistors are mainly used in BiCMOS technologies where circuit operation at very high frequencies is required. Silicon germanium heterojunction bipolar transistors (HBTs) have been produced with cut-off frequencies above 200GHz. Such transistors are ideal for use in radio frequency circuits in mobile communications products. Another important application is optical communications, where SiGe HBTs have been used to produce circuits that operate at 40Gbit/s. In all these applications, the rf performance can be significantly improved if the HBTs are produced on Silicon-On-Insulator substrates. HBTs on SOI is a new research field and only two other groups around the world have reported HBT on insulator devices. At Southampton, a novel growth process has been developed that combines selective growth of the Si collector with non-selective growth of the SiGe base and the Si cap. This process has the advantage of simplicity, since it halves the number of epitaxy steps needed to produce an HBT and eliminates the requirement for LOCOS or shallow trench isolation. SiGe HBTs have been successfully produced on SOI substrates using this combined selective/non-selective growth process. The inclusion of carbon in the SiGe base is currently being investigated, since it reduces boron transient enhanced diffusion and hence allows thinner bases to be produced.
Primary investigator
- pa
Secondary investigator
- hawem99r
Partners
- Queens University Belfast
- University of Liverpool
- University of Surrey
- Imperial College, University of London
Associated research group
- Nano Research Group
- Theme:
- Control Systems
- Funding:
- EPSRC
A theoretical investigation into the performance and robustness of nonlinear controllers.
Primary investigator
- mcf
Secondary investigator
- wb
Associated research group
- Information: Signals, Images, Systems Research Group
- Date:
- 2003-2006
- Themes:
- Quantum Electronics and Spintronics, Silicon Electronic Devices, Nanomaterials and Dielectrics
- Funding:
- EPSRC (MOTT grant)
Progress in integrated circuit (IC) technology has been achieved by reduction in the total area of individual transistors, resulting in an increase of speed accompanied by dramatic increase in density of device and interconnect integration. However, the metal oxide semiconductor field-effect transistor (MOSFET) has physical limits for reduction due to both short-channel effects, and the size of the area taken up by source and drain contacts and doping wells. To overcome these limits and to realize even smaller transistors, a device based on a novel operating principle is required. Furthermore, the introduction of high-k dielectrics and metal gates renders obsolete one of the key elements of Si technology scaling, the thermal growth of silicon dioxide as the gate insulator. A revolutionary non-Si based transistor might hence have a real shot at replacing CMOS technology.
The proposed metal oxide tunnel transistor (MOTT) is a device in which the tunnel probability through an insulating layer is modulated by a gate electrode. Source and drain of the device are metallic and no semiconductors are required in the process. This means that the source and drain contact areas are minimized and that no short channel effects can exist. High speed operation is expected since no minority carriers are involved. Furthermore the transistor can be grown on flexible substrates, and it is imaginable that three-dimensional circuits can be developed.
Primary investigator
Secondary investigators
- lhc02r
- km2
Associated research groups
- Nano Research Group
- Southampton Nanofabrication Centre
- Date:
- 2003-2011
- Theme:
- Nanoelectronics
- Funding:
- EU (SIGMOS), EPSRC (vertical MOSFET grant)
Over the past 20 years, the channel length of MOS transistors has halved at intervals of approximately every two or three years, which has led to a virtuous circle of increasing packing density (more complex electronic products), increasing performance (higher clock frequencies) and decreasing costs per unit silicon area. To continue on this path, Research is underway at Southampton University to investigate an alternative method of fabricating short-channel MOS transistors, socalled Vertical MOSFET's. In these devices the channel is perpendicular to the wafer surface in stead of in the plane of the surface. Vetical MOSFET's have three main advantages:
- First, the channel length of the vertical MOS transistor is not defined by lithography. This means no requirements for post-optical lithography techniques such as x-ray, extreme ultra-violet, electron projection lithography, ion projection lithography or direct write e-beam which are possibly prohibitively expensive.
-
Second, Vertical MOS transistors are easily made with both front gate and back gate.
Using this technology doubles the channel width per transistor area. Combined with easier design
rules, this leads to an increase of packing density of at least a factor of four as compared
to horizontal transitors.
One step further, is the use of very narrow pillars with the gate surrounding the entire pillar. This way, fully depleted transistors can be produced which have all the advantages of SOI transistors. - Third advantage of the vertical MOSFET is the possibility to prevent short channel effects from dominating the transitor by adding processes that are not easily realised in horizontal transistors, such as a polysilicon (or polySiGe) source to reduce parasitic bipolar effects or a dielectric pocket to reduce drain induced barrier lowering (dibl).
Primary investigators
Secondary investigators
- vdk99r
- tu
- eg02r
Partner
- University of Liverpool
Associated research groups
- Nano Research Group
- Southampton Nanofabrication Centre
- Theme:
- MEMs and NEMs
- Funding:
- EPSRC
The project is concerned with the investigation of using micromachining techniques to design and realise Atom Chips. Clouds of atoms are levitated by magnetic fields above a silicon surface and guided along pathways. This is achieved by passing current through wires creating the magnetic fields. Additionally, the atoms clouds interact with photons which are brought to the atom clouds by optical waveguides. Applications are for highly sensitive interferometers, gates for quantum computers and gravity measurement sensors. MEMS fabrication techniques to be developed require to electroplate the high-current density wires on a silicon substrate and a micromirror actuated by a comb drive which is required for the optical readout. Another important aspect is the integration of optical fibres on the same chip. These fibres can be used for novel modulation techniques used in optical data communications systems.
Primary investigator
- mk1
Secondary investigator
- Prof. Ed Hinds (Imperial College)
Partner
- Imperial College
Associated research groups
- Nano Research Group
- Southampton Nanofabrication Centre
- Theme:
- MEMs and NEMs
- Funding:
- EPSRC
Micromachined actuators have a range of applications, e.g. for the integration of an Atomic Force Microscope (AFM) on a single chip, novel lithography techniques, micro-switches, etc. The project investigates thermal actuators to realise movement along three axes. A micro-fabrication process has been developed that allows to produce in-plane bimorphs consisting of aluminium and silicon. An actuator stage is being designed having a platform on which an atomically sharp tip can be placed. This can be used for scanning an area of a sample, thus obtaining an image of the sample topology. The actuators incorporate piezo-resistors which result in a resistance change proportional to strain due to surface-tip interaction.
Primary investigator
- agre
Associated research groups
- Nano Research Group
- Southampton Nanofabrication Centre
- Theme:
- MEMs and NEMs
- Funding:
- EPSRC
A variety of microfluidic devices are being investigated such as micro-pumps which are capable of pumping fluids and gases, micro-flowsensors and mixers. These devices can be integrated on a microfluidic circuit board to realise systems that are suitable for a range of biological and chemical applications. Examples include polymerese chain reaction chambers (PCR) for DNA amplification, fully automated DNA analysis systems, chemical synthesis reactors and micro-Total Analysis Systems.
Primary investigators
- Professor Alan Evans
- Tracy Melvin
- James Wilkinson
Associated research groups
- Nano Research Group
- Optoelectronics Research Centre
- Theme:
- MEMs and NEMs
- Funding:
- Melexis, EPSRC
Novel concepts and approaches for micromachined inertial sensors such are accelerometers and gyroscopes are investigated. A micromachined disk will be levitated by electrostatic forces which can sense acceleration along three axes. If the disk is spun about its main axis, it concurrently can sense angular rotation about the two axes. The aim of the project is to design a five-degree of freedom inertial sensor. Furthermore, intelligent interface and closed loop control strategies for inertial sensors are being investigated. The principle relies on an electro-mechanical sigma-delta modulator loop; this approach results in a digital sensor which can directly interface to a DSP and facilitates smart sensors.
Primary investigators
Secondary investigator
- yd
Partner
- Melexis
Associated research groups
- Nano Research Group
- Southampton Nanofabrication Centre
- Date:
- 2000-2002
- Theme:
- Pervasive Computing and Networks
- Funding:
- JISC
This Internet 2 collaborative IPv6 deployment study project was led by Southampton and also featured Lancaster University and UCL. The project covered eight areas of study, from IPv6 routing and addressing through to transition and integration techniques. Overseen by UKERNA, the project has led to a UK IPv6 pilot for IPv6 on JANET (the UK academic network) and to all partners' participation in the 6NET project.
Primary investigator
Secondary investigator
Partners
- UKERNA
- UCL
- Lancaster
Associated research group
- Intelligence, Agents, Multimedia Group