Electronics and Computer Science (ECS), University of Southampton

Electronics and Computer Science (ECS)

Professor Peter Ashburn

Photograph of Prof Peter Ashburn
http://widgets.ecs.soton.ac.uk/image.php?id=person_37&maxw=250&maxh=300&corners=0&edge=1&checksum=21b950da59268f0412697ee2672ed41bPhotograph of Prof Peter Ashburn
Professor Peter Ashburn

ECS, Faculty of Physical Sciences and Engineering
University of Southampton
Southampton, United Kingdom. SO17 1BJ

Position: Academic staff in Nano Research Group
Extension: 22886
Telephone: Work (Voice): +44 (0)23 8059 2886
Fax: Work (Fax): 023 8059 3029
Email: pa@ecs.soton.ac.uk
URI: http://id.ecs.soton.ac.uk/person/37 [browse]

Peter works with:

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Interests: behaviour of fluorine in silicon, carbon nanotube fets, nanowire transistors, silicon-compatible carbon nanotube growth, surround gate vertical mosfets, transistor-in-a-grain technology for ultimate cmos, vacancy engineering for boron diffusion suppression

Biography

Born in Rotherham, Yorkshire, I studied for my bachelor and doctoral degrees in electrical and electronic engineering at the University of Leeds, England, graduating in 1974. I have always been fascinated by the interactions at the interface between industrial and university research, and this fascination is an important motivation for my research.

My career began at the Philips Research Labs, where I gained valuable experience of silicon bipolar and MOS technology and electron beam lithography. After moving to the University of Southampton as a lecturer, I worked on polysilicon emitters in collaboration with Plessey. This work led to the development of a self-aligned, double polysilicon bipolar technology that is still in production today. The next phase of my career was a series of research projects on the applications of low temperature silicon epitaxy and silicon-germanium epitaxy, which led to work on SiGe heterojunction bipolar transistors. This research theme has been very fruitful and highly collaborative, involving extensive interactions with British Telecom, Zarlink, Centre National d’Etudes des Telecommunications, and ST Microelectronics.

As channel lengths of MOS transistors move to nanometer dimensions, it is clear that major innovations will be needed to the architecture of MOS transistors. To control short channel effects, technologies will be needed for double gates, raised sources and drains, surround gates, vertical channels and ultimately 3D integrated structures and hence my research team is actively pursuing these possibilities. As part of this research, I have managed the European Union SIGMOS project, which had the goals of producing 50nm MOSFETs with raised sources & drains, SiGe p-channels, and strained silicon n-channels using Si:C and low capacitance vertical MOSFETs. These topics were pursued through the European Union SINANO project and are currently being pursued through a UK-funded project on vertical MOSFETs for RF applications.

I am currently a professor in the Nano Group of the School of Electronics and Computer Science. I have published over 250 academic papers and have written two text books.

Qualifications

BSc, PhD, CEng, FIET, MIEEE, MIOP

Consultancy

  • Sarnoff Corp, Princeton, USA;
  • Thermo VG Semicon, E Grinstead;
  • Fairchild Semiconductor, Portland,
  • USA; Chartered Semiconductor, Singapore;
  • Seagate Microelectronics, Livingston, Scotland;
  • National Semiconductor, Greenock, Scotland;
  • GEC, Wembley, England;
  • Plessey, Caswell, England;
  • Sinclair Research, Cambridge, England

Conferences Attended

  • European Solid State Device Research Conference,
  • European Materials Research Society Conference,
  • International Electron Devices Meeting,
  • Symposium on Diagnostics & Yield,
  • International Conference on the Science and Application of Nanotubes

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